Compact model for multiple-gate junctionless FETs

Abstract

A novel concept of a field effect transistor called a junctionless field-effect-transistor (JL-FET) was recently introduced along with its extremely simple fabrication process due to the absence of the formation of junctions. Its high compatibility with the current CMOS technology and the easy fabrication process makes it one of the most promising alternatives to the conventional inversion-mode FET (IM-FET). For better control of the JL-FETs’ channel, a newly proposed device architecture having a multiple-gate (Mug) structure has become available to the standard CMOS technologies. Thus, it is timely to establish a compact model for the Mug-JL-FETs, which would provide us fast computation time for circuit simulators. In this context, this work presents a compact model of charge and drain current for JL-FETs. The modeling process starts from the parabolic potential profile assumption. The resulting mobile charge equations for the Mug-JL-FETs could be classified into two coordinates: Cartesian and Cylindrical coordinates. With superposition of the two models based on the different coordinates, more realistic shaped channels such as elliptical channel etc. could be also considered. The drain current could be obtained through the so-called decoupling method. This work also proposes the generalized threshold voltage model of tied and untied double-gate JL-FETs for a symmetric and asymmetric structure, which cannot be considered in the abovementioned compact charge model since the same gate bias is applied in the Mug-JL-FET model. The proposed models have been compared with the numerical simulation results and showed good agreement throughout.