Energy-efficient partial LDPC decoding algorithm and its implementation for NAND flash-based storage systems

Abstract

A new decoding algorithm for the low-density parity-check (LDPC) codes is presented to lower the energy consumption of NAND flash-based storage systems. The maximum-effort decoding with the full parity-check matrix (H-matrix) is inefficient in the beginning stage, because the NAND flash channel is relia-ble at that time. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by con-sidering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Compared to the conventional method that decodes with the full H-matrix, the proposed algorithm reduces up to 67% memory accesses, reducing the energy consumption of a LDPC decoder significantly. The decoding latency is also reduced to 35.5% of the conventional decoding architecture. The decoding architecture to realize the proposed algorithm is also presented and the decoding architecture adopts the proposed algorithm is implemented in 65nm CMOS process. According to the imple-mentation results, the proposed algorithm reduces of the energy consumed for producing one-bit-output to 37.7% and the boosts the decoding throughput to 2.7 times up compared to the conventional algorithm.