DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Joon Yeong | ko |
dc.contributor.author | Han, Kwang Seok | ko |
dc.contributor.author | Kim, Tae Ho | ko |
dc.contributor.author | Lee, Sang Eun | ko |
dc.contributor.author | Lee, Jeong Sup | ko |
dc.contributor.author | Yoon, Tae Hun | ko |
dc.contributor.author | Park, Jin Ho | ko |
dc.contributor.author | Bae, Hyeon Min | ko |
dc.date.accessioned | 2016-04-18T04:59:40Z | - |
dc.date.available | 2016-04-18T04:59:40Z | - |
dc.date.created | 2015-11-20 | - |
dc.date.created | 2015-11-20 | - |
dc.date.created | 2015-11-20 | - |
dc.date.issued | 2015-09-29 | - |
dc.identifier.citation | IEEE Custom Integrated Circuits Conference (CICC) 2015, pp.1 - 4 | - |
dc.identifier.issn | 0886-5930 | - |
dc.identifier.uri | http://hdl.handle.net/10203/204333 | - |
dc.description.abstract | A phase interpolator (PI)-based 10 × 10 Gb/s bootstrap transceiver for reference-less and lane-independent operation is presented. PI output clock signals that are phase locked to the input data are used for the voltage-controlled oscillator (VCO) frequency locking. The VCO clock signal is then redistributed to the PIs, which triggers bootstrapping between the VCO and PIs. Entire lanes operate independently as in VCO-based parallel reference-less designs, but without performance penalties and with power and area savings. The measured recovered-data jitter in each lane is 0.93 psrms and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology, having receiver and transmitter figure-of-merits (mW/Gb/s) of 2.03 and 2.13, respectively. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | A power-and-area efficient 10 x 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation | - |
dc.type | Conference | - |
dc.identifier.wosid | 000369107500016 | - |
dc.identifier.scopusid | 2-s2.0-84959250002 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 1 | - |
dc.citation.endingpage | 4 | - |
dc.citation.publicationname | IEEE Custom Integrated Circuits Conference (CICC) 2015 | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | DoubleTree Hotel, San Jose, California | - |
dc.contributor.localauthor | Bae, Hyeon Min | - |
dc.contributor.nonIdAuthor | Han, Kwang Seok | - |
dc.contributor.nonIdAuthor | Kim, Tae Ho | - |
dc.contributor.nonIdAuthor | Lee, Sang Eun | - |
dc.contributor.nonIdAuthor | Lee, Jeong Sup | - |
dc.contributor.nonIdAuthor | Park, Jin Ho | - |
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