Results 1-10 of 13 (Search time: 0.004 seconds).
NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
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Phase Assignment for the Synthesis of Low Power Domino Circuits Priyadasan Patra; Unni Narayanan; Taewhan Kim, ELECTRONICS LETTERS, v.37, no.13, pp.814 - 816, 2001-06 | |
Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim; Sung-Mo Kang, ELECTRONICS LETTERS, v.37, no.13, pp.813 - 814, 2001-06 | |
A New Approach to the Multiport Memory Allocation Problem in Data Path Synthesis Taewhan Kim; C.L. Liu, INTEGRATION-THE VLSI JOURNAL, v.19, no.3, pp.133 - 160, 1995-10 | |
A Practical Approach to the Synthesis of Arithmetic Circuits using Carry-Save Adders Taewhan Kim; Junhyung Um, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.19, no.5, pp.615 - 624, 2000-05 | |
Circuit Optimization using Carry-Save-Adder Cells Taewhan Kim; William Jao; Steve Tjiang, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.17, no.10, pp.974 - 984, 1998-10 | |
A Scheduling Strategy for Tasks with Precedence and Conditional Execution Hideroni Nakazato; Jane W. S. Liu; Taewhan Kim, TRANSACTIONS OF INFORMATION PROCESSING SOCIETY OF JAPAN, v.36, no.9, pp.2161 - 2174, 1995-09 | |
Domino Logic Synthesis based on Implication Graph for Set of Mandatory Assignments Ki-Wook Kim; Taewhan Kim; C.L. Liu; Sung-Mo Kang, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.21, no.2, pp.232 - 240, 2002-02 | |
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits Junhyung Um; Taewhan Kim, IEEE TRANSACTIONS ON COMPUTERS, v.50, no.3, pp.215 - 233, 2001-03 | |
A Scheduling Algorithm for Conditional Resource Sharing - A Hierarchical Reduction Approach Taewhan Kim; Noritake Yonezawa; Jane W.S. Liu; C.L. Liu, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.13, no.4, pp.425 - 438, 1994-04 | |
An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization Chaeryung Park; Taewhan Kim; C.L. Liu, VLSI DESIGN, v.11, no.4, pp.381 - 396, 2000 |
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