Browse "School of Electrical Engineering(전기및전자공학부)" by Title
Showing results 31001 to 31020 of 51627
| Power factor correction circuit for low-cost electronic ballast using current-source type push-pull resonant inverter Chae, G; Cho, Gyu-Hyeong, ELECTRONICS LETTERS, v.34, no.6, pp.501 - 502, 1998-03 |
| Power Factor Correction Method without Input Current Sensor 정용석; 문건우; 노정욱; 윤명중, 1996년 전력전자학술대회, pp.85 - 88, KIPE, 1996-07 |
| Power Factor Correction Technique of Boost Converter Based on Average Model 정영석; 문건우; 이준영; 윤명중, 전력전자학회 창립기념 학술발표회, pp.85 - 88, 전력전자학회, 1996 |
| Power gating and supply control for low standby leakage power of VLSI circuits Heo, S; Kim, HO; Shin, Youngsoo, Symposium on Low-Power and High-Speed Chips (COOL Chips), pp.305 - 307, IEEE, 2006-04 |
| Power Gating: Circuits, Design Methodologies, and Best Practice for Standard-Cell VLSI Designs Shin, Young-Soo; Seomun, Jun; Choi, Kyu-Myung; Sakurai, Takayasu, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.15, no.4, 2010-09 |
| Power generating circuit and switching circuit Hong, Songcheol; Baek, Dong Hyun; Yun, Sun Woo; Park, Sung Hwan; Kim, Yu Sin, 2019-01-09 |
| Power integrity comparison of off-chip, on-interposer, on-chip voltage regulators in 2.5D/3D ICs Kim, Subin; Cho, Kyungjun; Park, Shinyoung; Park, Hyunwook; Kim, Seongguk; Jeong, Seungtaek; Son, Kyungjune; et al, 2019 Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2019, Institute of Electrical and Electronics Engineers Inc., 2019-12 |
| Power integrity design of full wafer scale chip architecture for hyper-scale artificial intelligence training and inference computing = 초거대 인공지능 훈련 및 추론 컴퓨팅을 위해 전력 무결성을 고려한 풀 웨이퍼 스케일 칩 아키텍쳐 설계link Kim, Hyunwoo; 김현우; et al, 한국과학기술원, 2024 |
| Power Loading Using Order Mapping in OFDM Systems With Limited Feedback Choi, Eun H.; Choi, Wan; Andrews, Jeffrey G.; Womack, Baxter F., IEEE SIGNAL PROCESSING LETTERS, v.15, pp.545 - 548, 2008 |
| Power management device for energy harvesting 이상국; 임백민; 서정일; 노영석; 구현모, 2018-03-20 |
| Power Management IC With a Three-Phase Cold Self-Start For Thermoelectric Generators Tran-Dinh, Thinh; Pham, Hieu Minh; Pham-Nguyen, Loan; Lee, Sang-Gug; Le, Hanh-Phuc, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.68, no.1, pp.103 - 113, 2021-01 |
| Power Management Scheme Considering Priority in Wireless LAN Kwon, Sang Wook; Lee, Jung Ryun; Cho, Dong-Ho, IEEE VTS Vehicular Technology Conference : VTC, pp.1149 - 1153, IEEE, 2005-09 |
| Power management system in the microgrid with the proper electric vehicle data preprocessing Kim, Jangkyum; Kim, Nakyoung; Han, Jaeseob; Seo, Hyeonseok; Choi, Jun Kyun; Kim, J.; Kim, N.; et al, 11th International Conference on Information and Communication Technology Convergence (ICTC) - Data, Network, and AI in the age of Untact (ICTC), v.2020-October, pp.1748 - 1751, IEEE, 2020-10 |
| Power minimization for 2- and $3-V_{DD}$ digital circuits = 2중, 3중 전원이 공급되는 디지털 회로를 위한 전력 최소화link Ahn, Ki-Yong; 안기용; et al, 한국과학기술원, 2009 |
| Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming Kyung, Chong-Min; Ahn, Ki-Yong, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E92A, pp.2318 - 2325, 2009-09 |
| Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling Shin, In-Sup; Kim, Jae-Joon; Shin, Youngsoo, Asia South Pacific Design Automation Conference, pp.179 - 184, IEEE, 2014-01 |
| Power module and multi power supply apparatus having the same 윤명중; 김형석; 이재범; 박상현; 조제형; 성현욱; 박진식; et al, 2015-07-15 |
| Power module varying bias power and distributed power supply apparatus 문건우; 김정은; 이정남; 김덕유; 김돈식, 2016-05-17 |
| Power MOSFET의 설계 및 제작 = Design and fabrication of power MOSFETlink 박찬광; Park, Chan-Kwang; et al, 한국과학기술원, 1987 |
| Power network using standard cell, power gating cell, and semiconductor device using the power network 신영수, 2010-07-13 |
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