Browse "School of Electrical Engineering(전기및전자공학부)" by Title
Showing results 26241 to 26260 of 51623
| MOS CHARACTERISTICS OF NH3-NITRIDED N2O-GROWN OXIDES Yoon, Giwan; JOSHI, AB; KIM, J; KWONG, DL, IEEE ELECTRON DEVICE LETTERS, v.14, no.4, pp.179 - 181, 1993-04 |
| MOS characteristics of substituted Al gate on high-kappa dielectric Park, CS; Cho, Byung Jin; Kwong, DL, IEEE ELECTRON DEVICE LETTERS, v.25, no.11, pp.725 - 727, 2004-11 |
| MOS characteristics of synthesized HfAlON-HfO2 stack using AIN-HfO2 Park, CS; Cho, Byung Jin; Kwong, DL, IEEE ELECTRON DEVICE LETTERS, v.25, no.9, pp.619 - 621, 2004-09 |
| MOS CHARACTERISTICS OF ULTRATHIN NO-GROWN OXYNITRIDES BHAT, M; KIM, J; YAN, J; Yoon, Giwan; HAN, LK; KWONG, DL, IEEE ELECTRON DEVICE LETTERS, v.15, no.10, pp.421 - 423, 1994-10 |
| MOS logic network simulation with a swithch-level model = 스위치 레벨 모델을 이용한 MOS 논리 회로망의 시뮬레이션link Lee, Jae-Cheol; 이재철; et al, 한국과학기술원, 1982 |
| MOS 실리콘-액정 복합 Light Valve 권영세; 김충기; 송종인, 대한젼자공학회 추계 종합학술대회, 1981 |
| MOS 트랜지스터의 전압 - 전류 특성을 이용한 아나로그 곱셈기의 집적회로 구현 김충기, 대한전자공학회 CAD, 반도체, 재료 및 부품연구회 합동학술발표회, 1988 |
| MOS 트랜지스터의 전압-전류 특성을 이용한 아날로그 승적기의 집적회로 구현 = IC implementation of analog multiplier which have the voltage-current characteristric of MOSFETlink 송호준; Song, Ho-Jun; et al, 한국과학기술원, 1988 |
| MoS2 charge trap memory cell 특성 평가 신의중; 임이랑; 임종선; 황완식; 조병진, 제26회 한국반도체학술대회, DB하이텍, 한국반도체산업협회, 한국반도체연구조합, 2019-02-14 |
| MoS2-based 3D stackable charge-trap memory with AlN interface layer for reducing optical phonon scattering Bae, Sanggeun; Oh, Jungyeop; Kang, Mingu; Choi, Sung-Yool, IEEE EDTM 2023, IEEE, 2023-03-09 |
| MoS2-based floating gate memory with metal nanoparticle and polymer tunneling dielectric layer Woo, Myung Hun; Jang, Byung Chul; Choi, Jun Hwan; Shin, Gwang Hyuk; Seong, Hye Jeong; Im, Sung Gap; Choi, Sung Yool, ICAMD 2015, ICAMD 2015, 2015-12-09 |
| mOS: A Reusable Networking Stack for Flow Monitoring Middleboxes Jamshed, Muhammad Asim; Moon, Younggyoun; Kim, Donghwi; Han, Dongsu; Park, Kyoung-Soo, 14th USENIX Symposium on Networked Systems Design and Implementation (NSDI), USENIX Association, 2017-03-27 |
| $MoS_2/WSe_2$ 이종접합 기반의 P형 터널링 전계효과 트랜지스터 = P-type tunneling field effect transistor based on $MoS_2/WSe_2$ heterojunctionlink 전현배; 최성율; et al, 한국과학기술원, 2019 |
| Mosaic: Extremely Low-resolution RFID Vision for Visually-anonymized Action Recognition Shim, Seungwoo; Shin, Hyeonho; Cho, Myeongkyun; Lee, Youngki; Shin, Jinwoo; Kim, SongMin, 22nd ACM/IEEE International Conference on Information Processing in Sensor Networks, IPSN 2023, pp.247 - 260, Association for Computing Machinery, Inc, 2023-05-12 |
| MOSA를 이용한 다목적함수 최적화 및 성능평가 알고리즘 개발 = Multiobjective optimization using simualated annealing and multiobjective metricslink 이선영; Lee, Sun-Young; et al, 한국과학기술원, 2006 |
| MOSEFT source and drain structures for high density CMOS integrated circuits = 고집적 CMOS 집적회로를 위한 MOSEFT 의 소오스와 드레인 구조link Oh, Choon-Sik; 오춘식; et al, 한국과학기술원, 1986 |
| MOSFET Characteristics for Terahertz Detector Application From On-Wafer Measurement Kim, Suna; Park, Dae-Woong; Choi, Kyoung-Young; Lee, Sang-Gug, IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, v.5, no.6, pp.1068 - 1077, 2015-11 |
| MOSFET Device Originated Harmonic Distortion Analysis and Optimum Design Methodology for SOI SPDT RF Switch Im, D; Kim, B.-K.; Choi, J; Cho, Y; Kim, B; Lee, Kwyro, 2012 EuroSOI, IES, the Southern Electronics Institute, 2012-01 |
| MOSFET Device Originated Harmonic Distortion Analysis and Optimum Design Methodology for SOI SPDT RF Switch Im, D; Kim, B.-K.; Choi, J; Cho, Y; Kim, B; Lee, K, The 19th Korean Conference on Semiconductors (KCS2012), 2012-02-16 |
| MOSFET 회로설계를 위한 spice parameter의 추출 경종민; 김효식, 대한전자공학회 추계종합학술대회 , v.7, no.2, pp.13 - 15, 1984 |
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