Showing results 20001 to 20020 of 51627
Hankel-norm 을 이용한 극점을 유지하는 모델감소방법 Shin, Yong-Soub; Lee, Ju-Jang, 97 제어계측·자동화·로보틱스 연구회 합동학술발표회, pp.229 - 232, 대한전자공학회, 1997-03 |
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning Shin, Youngsoo; Shin, In-Sup; Baek, Donkyu; Kim, Duckhwan; Paik, Seungwhun, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.61, no.1, pp.146 - 159, 2014-01 |
Hard-information based majority-logic decoding method and structure for non-binary LDPC codes = 논바이너리 LDPC용 경정보 기반 다수결 논리 복호 방법과 구조link Yeo, Saedong; 여세동; et al, 한국과학기술원, 2016 |
HardsHeap: A Universal and Extensible Framework for Evaluating Secure Allocators Insu Yun; Woosun Song; Seunggi Min; Taesoo Kim, 28th ACM Conference on Computer and Communications Security (CCS '21), pp.379 - 392, ACM, 2021-11-16 |
HARDWARE ACCELERATOR FOR OUTLINE FONT GENERATION HWANG, GC; Park, In-Cheol; LEE, YT; LEE, TH; BAE, JH; Kyung, Chong-Min, IEICE TRANSACTIONS ON COMMUNICATIONS ELECTRONICS INFORMATION AND SYSTEMS, v.74, no.10, pp.3078 - 3082, 1991-10 |
Hardware Accelerator for Scalable Hangul Font Generation Hwang, G.C.; Lee, Y.T.; Park, In-Cheol; Lee, T. H.; Bae, J.H.; Kyung, Chong-Min, Joint Technical Conference on Citcuits/Systems, Computers and Communications, pp.246 - 250, 대한전자공학회, 1990 |
Hardware accelerator with output-bit-serial multiplication of data from MSB to LSB = 높은 자리부터 낮은 자리 순서로 출력을 생성하는 데이터 곱셈을 이용한 하드웨어 가속기link Moon, Byeongmin; 문병민; et al, 한국과학기술원, 2022 |
Hardware and algorithm co-optimization for graph neural network acceleration = 그래프 신경망 가속을 위한 하드웨어 및 알고리즘 최적화link Han, Yunki; 한윤기; et al, 한국과학기술원, 2021 |
Hardware and software requirements for a picture archiving and communication systems diagnostic workstations Haynor, D.R.; Smith, D.V.; Park, HyunWook; Kim, Y., JOURNAL OF DIGITAL IMAGING, v.5, no.2, pp.107 - 117, 1992-05 |
Hardware and software systems for accelerating large-scale deep learning recommendation models = 딥러닝 기반 대규모 추천시스템 가속을 위한 하드웨어 및 소프트웨어 시스템link Kwon, Youngeun; 권영은; et al, 한국과학기술원, 2024 |
Hardware architecture and optimization of sliding window based pedestrian detection on FPGA for high resolution images by varying local features Khan, Asim; Khan, Muhammad Umar Karim; Bilal, Muhammad; Kyung, Chong-Min, 23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, pp.142 - 148, IEEE Computer Society, 2015-10-06 |
Hardware architecture exploration of IEEE 802.11n receiver using SystemC transaction level modeling Lee J.; Park, Sin Chong, 9th International Conference on Advanced Communication Technology, ICACT 2007, v.3, pp.1707 - 1710, 2007-02-12 |
Hardware design of CP length detector for the WirelessMAN-OFDM system Kim T.; Park S.; Lee S.; Park, Sin Chong, 2006 International Symposium on Intelligent Signal Processing and Communications, ISPACS'06, pp.474 - 476, 2006-12-12 |
Hardware Discrete Event System Specification(HDEVS) for VLSI Implementation Park, Kyu Ho; Lee, Y.M., The Fifth Asia Pacific Conference on Hardware Description Languages, 1998 |
Hardware Efficient Implementation Techniques of List Sphere Decoder Park, Sin Chong, APWCS 2006 |
Hardware implementation of the elementary function = 초월함수의 하드웨어 구현link Seo, Bong-Jin; 서봉진; et al, 한국과학기술원, 1997 |
Hardware implementation of the programmable IIR digital filter with one high speed multiplierlink Lee, Ho-Soo; 이호수; et al, 한국과학기술원, 1977 |
Hardware module interchange format for HW/SW co-simulation = 하드웨어/소프트웨어 통합시뮬레이션을 위한 hardware module interchange formatlink Kim, Jun-Kyoung; 김준경; et al, 한국과학기술원, 1999 |
Hardware optimizations for advanced forward error correction = 고급 순방향 오류정정을 위한 하드웨어 최적화link Lee, Youngjoo; 이영주; et al, 한국과학기술원, 2014 |
Hardware-Centric Vision Processing for Mobile IoT Environment Exploiting Approximate Graph cut in Resistor Grid Choi, Yeongjae; Park, Jun-Seok; Kim, Lee-Sup, 17th IEEE Winter Conference on Applications of Computer Vision (WACV), IEEE Computer Society, IEEE Biometrics Council, 2017-03 |
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