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Showing results 1 to 5 of 5

1
A 200-MHZ 13-MM(2) 2-D DCT MACROCELL USING SENSE-AMPLIFYING PIPELINE FLIP-FLOP SCHEME

MATSUI, M; HARA, H; UETANI, Y; Kim, Lee-Sup; NAGAMATSU, T; WATANABE, Y; MATSUDA, K; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.29, no.12, pp.1482 - 1490, 1994-12

2
A CU-Level Rate and Distortion Estimation Scheme for RDO of Hardware-Friendly HEVC Encoders Using Low-Complexity Integer DCTs

Lee, Bumshik; Kim, Mun-Churl, IEEE TRANSACTIONS ON IMAGE PROCESSING, v.25, no.8, pp.3787 - 3800, 2016-08

3
A mode-changeable 2-D DCT/IDCT processor for digital VCR

Paek, SK; Kim, JH; Kwon, BS; Chung, DH; Kim, Lee-Sup, IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v.42, no.3, pp.606 - 616, 1996-08

4
Hardware-software co-implementation of a H.263 video codec

Jang, SK; Kim, SD; Lee, J; Choi, GY; Ra, Jong Beom, IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v.46, no.1, pp.191 - 200, 2000-02

5
KAIST image computing system (KICS): A parallel architecture for real-time multimedia data processing

Jeon, J; Kim, HS; Choi, G; Park, HyunWook, JOURNAL OF SYSTEMS ARCHITECTURE, v.46, no.15, pp.1403 - 1418, 2000-12

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