Showing results 1 to 5 of 5
A CNN Inference Accelerator on FPGA with Compression and Layer-Chaining Techniques for Style Transfer Applications Kim, Suchang; Jang, Boseon; Lee, Jaeyoung; Bae, Hyungjoon; Jang, Hyejung; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.70, no.4, pp.1591 - 1604, 2023-04 |
Area-efficient QC-LDPC decoding architecture with thermometer code-based sorting and relative quasi-cyclic shifting = 온도계 코드 기반 정렬 및 상대적 준순환 회전을 사용한 면적 효율적인 QC-LDPC 복호 구조link Jang, Boseon; Park, In-Cheol; et al, 한국과학기술원, 2023 |
Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting Jang, Boseon; Jang, Hyejung; Kim, Sungho; Choi, Kangjoon; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.71, no.6, pp.2897 - 2910, 2024-06 |
High-Speed Counter with Novel LFSR State Extension Bae, Hyungjoon; Hyun, Yujin; Kim, Suchang; Park, Sangsoo; Lee, Jaeyoung; Jang, Boseon; Choi, Suyoung; et al, IEEE TRANSACTIONS ON COMPUTERS, v.72, no.3, pp.893 - 899, 2023-03 |
Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard Lee, Seongjin; Park, Sangsoo; Jang, Boseon; Park, In-Cheol, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.69, no.5, pp.2035 - 2048, 2022-05 |
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