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Showing results 7 to 13 of 13

7
Modeling and analysis of LC-VCO performance degradation and shielding for tsv noise coupling in 3D IC = 3차원 집적회로에서 실리콘 관통 비아의 잡음전달과 LC-VCO 성능 저하의 모델링 및 분석과 차폐에 대한 연구link

Lim, Jae-Min; 임재민; et al, 한국과학기술원, 2014

8
Modeling and analysis of noise coupling and RF sensitivity in through-silicon-via (TSV) silicon interposer = 실리콘 관통 비아 실리콘 인터포져에서의 노이즈 커플링 모델링과 RF감도 해석link

Yoon, Ki-Hyun; 윤기현; et al, 한국과학기술원, 2010

9
Modeling and analysis of power distribution network in 2.5D and 3D IC based on segmentation method and target impedance considering current spectrum = 구조분할 방법과 전류 스펙트럼에 기반한 목표 임피던스를 이용한 2.5차원/3차원 반도체에서 전력분배망의 모델링 및 분석link

Kim, Youngwoo; 김영우; et al, 한국과학기술원, 2015

10
Temperature-dependent through-silicon via (TSV) model and isolation characteristics = 온도에 의존하는 관통 실리콘 비아 모델과 아이솔레이션 특성link

Lee, Man-Ho; 이만호; et al, 한국과학기술원, 2012

11
Through-Silicon Via Capacitance-Voltage Hysteresis Modeling for 2.5-D and 3-D IC

Kim, Dong-Hyun; Kim, Youngwoo; Cho, Jong-Hyun; Bae, Bumhee; Park, Junyong; Lee, Hyunsuk; Lim, Jaemin; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.7, no.6, pp.925 - 935, 2017-06

12
Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs

Song, Eun-Seok; Koo, Kyoung-Choul; Pak, Jun-So; Kim, Joung-Ho, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.3, no.9, pp.1467 - 1480, 2013-09

13
Vertical Noise Coupling From On-Chip Switching-Mode Power Supply in a Mixed-Signal Stacked 3-D-IC

Koo, Kyoung-Choul; Kim, Myung-Hoi; Kim, Jonghoon J.; Kim, Joung-Ho; Kim, Ji-Seong, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.3, no.3, pp.476 - 488, 2013-03

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