Browse "School of Electrical Engineering(전기및전자공학부)" by Type Conference
Showing results 4561 to 4580 of 22776
| Architectural trade-off of Viterbi Decoder using Modified Register Exchanged State-mapping method Park, Sin Chong, ITC-CSCC 2005, pp.125 - 126, 2005-07-01 |
| Architecture and algorithm for high precision image rejection and spurious rejection mixers using digital compensation Kim, Y.; Shin, S.; Lee, Kwyro, IEEE MSS-S International Microwave Symposium Digest, pp.799 - 802, IEEE, 2002-06-02 |
| Architecture and Algorithm for High Prejection and Spurious Rejection Mixers Using Digital Compensation Lee, Kwyro; Kim, Y.; Shin, S., 2002 IEEE MTT-S, pp.799 - 802, 2002 |
| Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000 Rhu, M.; Park, In-Cheol, 2009 IEEE International Conference on Image Processing, ICIP 2009, pp.2665 - 2668, 2009-11-07 |
| Architecture for multi-processor SoC platform using dedicated channels Lee G.; Park, Sin Chong, Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005, v.2005, pp.525 - 529, 2005-07-20 |
| Architecture level simulation of IEEE 802.11n MAC using systemc Yoon S.-R.; Park, Sin Chong, 5th IASTED Asian Conference on Communication Systems and Networks, AsiaCSN 2008, pp.46 - 49, 2008-04-02 |
| Architecture of broadband personal communication network Kim, Duk Kyung; Lee, Seung Joon; Choi, Dae Woo; Sung, Dan Keun, Proceedings of the 1996 7th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC'96. Part 3 (of 3), v.2, pp.603 - 607, 1996-10-15 |
| Architecture of Multi Cloud Resource Broker in Cloud Federation Kang, Dong Ki; Kim, Byung Sang; Kim, Seong Hwan; Youn, Chan-Hyun, 2012 International Exposition Yeosu Korea, International Conference on Information Technology(YSEC 2012), v.1, Korea Information Processing Society, 2012-04-27 |
| Architecture selection of a flexible DSP core using reconfigurable system software Lee, Jong-Yeol; Lee, Dea-Hyun; Kim, Jong-Sun; Yoon, Hyun-Dhong; Kyung, Chong-Min; Park, Kyu Ho; Lee, Yong-Hoon; et al, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6), pp.37 - 40, IEEE, 1998-05-31 |
| Archiving of meaningful scenes for personal TV terminals Jin, S.H.; Cho, J.H.; Ro, YongMan; Lee, H.K., Internet Imaging VII, v.6061, pp.0 - 0, 2006-01-18 |
| ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory Seo, Jin-O; Seok, Mingoo; Cho, SeongHwan, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.258 - 260, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
| Arctangent processor design for the frequency offset estimation of IEEE 802.16D wirelessMAN-OFDM system Kim T.; Park, Sin Chong, 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, pp.199 - 203, 2007-10-17 |
| Arctangent Processor Design for the Frequency Offset Estimation of IEEE 802.16d WirelessMAN-OFDM System Park, Sin Chong, ITC-CSCC2007 |
| Are different types of photon-pair sources equally indistinguishable in silicon photonics? Baldazzi, Alessio; Lee, Jong-Moo; Sanna, Matteo; Azzini, Stefano; Ahn, Joon Tae; Lee, Myung Lae; Sohn, Youngik; et al, Integrated Photnoics Resaerch, Silicon and Nanophotonics 2023, Optica Publishing Group 2023, 2023-07-10 |
| Area and power efficient 10-bit column driver with interpolating DAC and push-pull amplifier for AMLCDs Lee, H.-M.; Son, Y.-S.; Jeon, Y.-J.; Jeon, J.-Y.; Jung, S.-C.; Cho, Gyu-Hyeong, 2008 SID International Symposium, pp.889 - 891, 2008-05-20 |
| Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems Kim, T.-H.; Park, In-Cheol, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.111 - 112, IEEE, 2008-03-21 |
| Area efficient neuromorphic circuit based on stochastic computation 윤기원; 최수형; 신영수, 한국반도체학술대회, 대한전자공학회, 2017-02-15 |
| Area efficient neuromorphic circuit based on stochastic computation Yoon, Kiwon; Choi, Suhyeong; Shin, Youngsoo, 13th International SoC Design Conference, ISOCC 2016, pp.73 - 74, Institute of Electrical and Electronics Engineers Inc., 2016-10-23 |
| Area efficient pipelined VLSI implementation of list sphere decoder Lee J.; Park, Sin Chong, 2006 Asia-Pacific Conference on Communications, APCC, 2006-08-31 |
| Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory Jin, Y; Shihab, M; Jung, Myoungsoo, MemoryForum, IEEE, 2014-06-14 |
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