ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory

Abstract

One of the notable trends in convolutional neural network (CNN) processor architecture is to embrace analog hardware to improve energy efficiency in performing multiply-and-accumulate (MAC). Prior works investigated charge redistribution in a capacitor array [4], [5], phase accumulation in oscillators [2], [6], and the integrator in a delta-sigma modulator [3]. However, these works suffer from two critical challenges. First, they all need frequent use of ADCs and DACs to store and access the large intermediate computation results, i.e. feature maps, to and from the digital SRAM. The energy consumption of such data conversion severely limits the overall energy efficiency. To mitigate it, [1] uses analog memory but only for temporary data and it still requires a large amount of data conversion for computing multiple layers of a CNN model. Second, analog circuits including analog memory inherently exhibit non-negligible variability. Important parameters such as comparator threshold voltage, oscillator frequency, etc., vary across process, voltage, and temperature (PVT), limiting the computing precision of analog hardware. It is critical to increase the tolerance to these variations. In this work, aiming to address these challenges, we propose ARCHON, an analog CNN processor featuring an analog neuronal computation unit (ANU) and an analog memory (AMEM). Designed to tolerate a large amount of PVT variations, ANU and AMEM can perform computations needed for a CNN model in the analog domain, across layers, without data conversions. Fabricated in 28nm CMOS, the proposed processor achieves a state-of-the-art energy-efficiency of 332.7TOPS/W (analog datapath) and 19.9TOPS/W (processor level), while maintaining the inference accuracy across supply voltage and temperature variations. © 2022 IEEE.