DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Han Joon | ko |
dc.contributor.author | Kim, Gwang Sun | ko |
dc.contributor.author | Kim, John Dongjun | ko |
dc.date.accessioned | 2015-05-15T08:24:59Z | - |
dc.date.available | 2015-05-15T08:24:59Z | - |
dc.date.created | 2015-05-10 | - |
dc.date.created | 2015-05-10 | - |
dc.date.created | 2015-05-10 | - |
dc.date.issued | 2012-06 | - |
dc.identifier.citation | 2012 3rd International Green Computing Conference (IGCC) | - |
dc.identifier.uri | http://hdl.handle.net/10203/198468 | - |
dc.description.abstract | While much research has been done using 2D mesh network as a baseline on-chip network topology, recent multi-core chips from vendors leverage a ring topology. In this work, we re-visit the topology comparison in on-chip networks and model the impact of on-chip network on overall performance while holding the entire chip power constant. We vary the amount of power allocated to the on-chip network and evaluate its impact on overall performance to determine a balanced system design. We show how the ring topology is efficient in current technology at 45nm but the scalability is limited as technology continues to scale and show how a simple hierarchical ring approach can provide a scalable solution. | - |
dc.language | English | - |
dc.publisher | 기타(Technical Co-Sponsored by IEEE Computer Society) | - |
dc.title | Scalable On-Chip Network in Power Constrained Manycore Processors | - |
dc.type | Conference | - |
dc.identifier.wosid | 000309942300034 | - |
dc.identifier.scopusid | 2-s2.0-84869484687 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 2012 3rd International Green Computing Conference (IGCC) | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | San Jose, CA | - |
dc.identifier.doi | 10.1109/IGCC.2012.6322278 | - |
dc.contributor.localauthor | Kim, John Dongjun | - |
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