Block-Wise Concatenated BCH Codes for NAND Flash Memories

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In this work, we consider high-rate error-control systems for storage devices using multi-level per cell (MLC) NAND flash memories. Aiming at achieving a strong error-correcting capability, we propose error-control systems using block-wise parallel/serial concatenations of short Bose-Chaudhuri-Hocquenghem (BCH) codes with two iterative decoding strategies, namely, iterative hard-decision decoding (IHDD) and iterative reliability based decoding (IRBD). It will be shown that a simple but very efficient IRBD is possible by taking advantage of a unique feature of the block-wise concatenation. For tractable performance analysis and design of IHDD and IRBD at very low error rates, we derive semi-analytic approaches. The proposed error-control systems are compared with various error-control systems with well-known coding schemes such as a product code, multiple BCH codes, a single long BCH code, and low-density parity-check codes in terms of page error rates, which confirms our claim: the proposed error-control systems achieve good tradeoffs between error-performance and complexity as compared to the traditional schemes and is also very favorable for implementation.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2014-04
Language
English
Article Type
Article
Keywords

TO-CELL INTERFERENCE; CYCLIC PRODUCT CODES; LDPC CODES; ERROR-CORRECTION; ARCHITECTURE; ALGORITHMS; DECODER

Citation

IEEE TRANSACTIONS ON COMMUNICATIONS, v.62, no.4, pp.1164 - 1177

ISSN
0090-6778
DOI
10.1109/TCOMM.2014.021514.130287
URI
http://hdl.handle.net/10203/189315
Appears in Collection
EE-Journal Papers(저널논문)
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