DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, Sung-gun | ko |
dc.contributor.author | Kim, Daeseong | ko |
dc.contributor.author | Choi, Jinho | ko |
dc.contributor.author | Ha, Jeongseok | ko |
dc.date.accessioned | 2014-09-01T07:40:28Z | - |
dc.date.available | 2014-09-01T07:40:28Z | - |
dc.date.created | 2014-06-09 | - |
dc.date.created | 2014-06-09 | - |
dc.date.created | 2014-06-09 | - |
dc.date.issued | 2014-04 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMMUNICATIONS, v.62, no.4, pp.1164 - 1177 | - |
dc.identifier.issn | 0090-6778 | - |
dc.identifier.uri | http://hdl.handle.net/10203/189315 | - |
dc.description.abstract | In this work, we consider high-rate error-control systems for storage devices using multi-level per cell (MLC) NAND flash memories. Aiming at achieving a strong error-correcting capability, we propose error-control systems using block-wise parallel/serial concatenations of short Bose-Chaudhuri-Hocquenghem (BCH) codes with two iterative decoding strategies, namely, iterative hard-decision decoding (IHDD) and iterative reliability based decoding (IRBD). It will be shown that a simple but very efficient IRBD is possible by taking advantage of a unique feature of the block-wise concatenation. For tractable performance analysis and design of IHDD and IRBD at very low error rates, we derive semi-analytic approaches. The proposed error-control systems are compared with various error-control systems with well-known coding schemes such as a product code, multiple BCH codes, a single long BCH code, and low-density parity-check codes in terms of page error rates, which confirms our claim: the proposed error-control systems achieve good tradeoffs between error-performance and complexity as compared to the traditional schemes and is also very favorable for implementation. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | TO-CELL INTERFERENCE | - |
dc.subject | CYCLIC PRODUCT CODES | - |
dc.subject | LDPC CODES | - |
dc.subject | ERROR-CORRECTION | - |
dc.subject | ARCHITECTURE | - |
dc.subject | ALGORITHMS | - |
dc.subject | DECODER | - |
dc.title | Block-Wise Concatenated BCH Codes for NAND Flash Memories | - |
dc.type | Article | - |
dc.identifier.wosid | 000335377000002 | - |
dc.identifier.scopusid | 2-s2.0-84899900252 | - |
dc.type.rims | ART | - |
dc.citation.volume | 62 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 1164 | - |
dc.citation.endingpage | 1177 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMMUNICATIONS | - |
dc.identifier.doi | 10.1109/TCOMM.2014.021514.130287 | - |
dc.contributor.localauthor | Ha, Jeongseok | - |
dc.contributor.nonIdAuthor | Cho, Sung-gun | - |
dc.contributor.nonIdAuthor | Choi, Jinho | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Error-correcting codes | - |
dc.subject.keywordAuthor | storage systems | - |
dc.subject.keywordAuthor | NAND flash memories | - |
dc.subject.keywordAuthor | concatenated codes | - |
dc.subject.keywordAuthor | Error-correcting codes | - |
dc.subject.keywordAuthor | storage systems | - |
dc.subject.keywordAuthor | NAND flash memories | - |
dc.subject.keywordAuthor | concatenated codes | - |
dc.subject.keywordPlus | TO-CELL INTERFERENCE | - |
dc.subject.keywordPlus | CYCLIC PRODUCT CODES | - |
dc.subject.keywordPlus | LDPC CODES | - |
dc.subject.keywordPlus | ERROR-CORRECTION | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | ALGORITHMS | - |
dc.subject.keywordPlus | DECODER | - |
dc.subject.keywordPlus | TO-CELL INTERFERENCE | - |
dc.subject.keywordPlus | CYCLIC PRODUCT CODES | - |
dc.subject.keywordPlus | LDPC CODES | - |
dc.subject.keywordPlus | ERROR-CORRECTION | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | ALGORITHMS | - |
dc.subject.keywordPlus | DECODER | - |
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