Suppression of power/ground inductive impedance and simultaneous switching noise using silicon through-via in a 3-D stacked chip package

Abstract

We have thoroughly investigated the advantages of a silicon through-via (STV) interconnection in decreasing the inductive impedance of a power distribution network (PDN) and suppressing simultaneous switching noise (SSN) in a 3-D stacked chip package. A double-stacked chip package with STV interconnections was fabricated and measured together with a similar double-stacked chip package with conventional bonding-wire interconnections. We successfully demonstrated that significant reduction of the inductive PDN impedance, from 1.66 nH to 0.79 nH, can be achieved by replacing the conventional bonding wires in the multiple-stacked chip package by STV interconnections. Furthermore, we have shown that the STV interconnections can considerably reduce high-frequency SSN, by more than 80%, compared to the conventional bonding-wire interconnections.