A pipeline architecture with 1-cycle timing error correction for low voltage operations

Cited 9 time in webofscience Cited 14 time in scopus
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Publisher
International Symposium on Low Power Electronics and Design
Issue Date
2013-09-05
Language
English
Citation

International Symposium on Low Power Electronics and Design, pp.199 - 204

DOI
10.1109/ISLPED.2013.6629294
URI
http://hdl.handle.net/10203/182654
Appears in Collection
EE-Conference Papers(학술회의논문)
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