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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

A pipeline architecture with 1-cycle timing error correction for low voltage operations

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dc.contributor.authorInsup Shinko
dc.contributor.authorJae-Joon Kimko
dc.contributor.authorJae-Joon Kimko
dc.contributor.authorShin, Youngsooko
dc.date.accessioned2013-12-06T01:05:20Z-
dc.date.available2013-12-06T01:05:20Z-
dc.date.created2013-10-02-
dc.date.created2013-10-02-
dc.date.issued2013-09-05-
dc.identifier.citationInternational Symposium on Low Power Electronics and Design, pp.199 - 204-
dc.identifier.urihttp://hdl.handle.net/10203/182654-
dc.languageEnglish-
dc.publisherInternational Symposium on Low Power Electronics and Design-
dc.titleA pipeline architecture with 1-cycle timing error correction for low voltage operations-
dc.typeConference-
dc.identifier.wosid000337238700034-
dc.identifier.scopusid2-s2.0-84889597890-
dc.type.rimsCONF-
dc.citation.beginningpage199-
dc.citation.endingpage204-
dc.citation.publicationnameInternational Symposium on Low Power Electronics and Design-
dc.identifier.conferencecountryCC-
dc.identifier.conferencelocationBejing, China-
dc.identifier.doi10.1109/ISLPED.2013.6629294-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorShin, Youngsoo-
dc.contributor.nonIdAuthorInsup Shin-
dc.contributor.nonIdAuthorJae-Joon Kim-
dc.contributor.nonIdAuthorJae-Joon Kim-
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