Real-time-aware shared cache architecture for multi-core systems

Abstract

Multi-core processors with shared L2 caches can improve performance and integrate several functions on a single chip in real-time systems. However, tasks running on different cores can incur many conflict misses in the shared L2 cache, resulting in performance unpredictability and in increased WCETs (Worst Case Execution Times) of real-time tasks. We propose a novel shared L2 cache architecture that can alleviate these problems. First, our shared L2 cache architecture is aware of instructions/data belonging to real-time tasks by adding a real-time indication bit to each L2 cache block. Second, it allocates portion of cache space to non-real-time tasks without incurring interferences to real-time tasks by developing a real-time-aware replacement policy. Our proposed shared L2 cache architecture can be combined with the conventional cache partitioning and Bankization schemes to support multiple real-time tasks and non-real-time task running simultaneously on multiple cores. Experimental results show that the performances of real-time tasks, which run together with non-real-time tasks on multi-core systems, are predictable and that their WCETs are lower than those by the conventional schemes.