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Showing results 1 to 6 of 6

1
Development and evaluation of 3-D SiP with vertically interconnected Through Silicon Vias (TSV)

Jang, DM; Ryu, C; Lee, KY; Cho, BH; Kim, Joungho; Oh, TS; Lee, Won-Jong; et al, 57th Electronic Components and Technology Conference 2007, ECTC '07, pp.847 - 852, IEEE, 2007-05-29

2
Effects of additives on the defects of electroplated copper via in 3D SiP

Lee, Won-Jong; Cho, BH; Jang, GH, UMRS-ICA-2006, 2006-09-10

3
Effects of electroplating parameters on the defects of copper via for 3D SiP

Cho, BH; Lee, Won-Jong; Lee, JH, IUMRS International Conference in Asia 2006, IUMRS-ICA 2006, v.124-126, no.PART 1, pp.49 - 52, 2006-09-10

4
Filling of very fine via holes for 3-D SiP by using ionized metal plasma sputtering and electroplating

Lee, Won-Jong; Cho, BH, ICEP (International Conference on electronics packaging) 2007, 2007-04-18

5
Filling of very fine via holes for three dimensional packaging by using ionized metal plasma sputtering and electroplating

Cho, BH; Yun, JJ; Lee, Won-Jong, International Conference on Electronic Materials and Packaging 2007, EMAP 2007, 123, 2007-11-19

6
Via filling for System in Packaging by using IMP, PVD, CVD, ALD and Electroplating

Lee, Won-Jong; Cho, BH; Moon, JS, Pan Pacific Microelectronics Symposium, 2006-01-17

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