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Recognition of Logic Diagrams by Identifying Loops and Rectilinear Polylines

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dc.contributor.authorKim, S.H.-
dc.contributor.authorSuh, J.W.-
dc.contributor.authorKim, JinHyung-
dc.date.accessioned2010-03-29T01:56:22Z-
dc.date.available2010-03-29T01:56:22Z-
dc.date.created2012-02-06-
dc.date.issued1993-10-
dc.identifier.citationProceedings of the Second International Conference on Document Analysis and Recognition, v.0, no.0, pp.0 - 0-
dc.identifier.urihttp://hdl.handle.net/10203/17386-
dc.languageENG-
dc.language.isoen_USen
dc.publisherProceedings of the Second International Conference on Document Analysis and Recognition-
dc.titleRecognition of Logic Diagrams by Identifying Loops and Rectilinear Polylines-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.volume0-
dc.citation.issue0-
dc.citation.beginningpage0-
dc.citation.endingpage0-
dc.citation.publicationnameProceedings of the Second International Conference on Document Analysis and Recognition-
dc.identifier.conferencecountryJapan-
dc.identifier.conferencecountryJapan-
dc.contributor.localauthorKim, JinHyung-
dc.contributor.nonIdAuthorKim, S.H.-
dc.contributor.nonIdAuthorSuh, J.W.-
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CS-Conference Papers(학술회의논문)
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