Exploring the Opportunity of Optimizing Sequencing Elements in ASIC Designs

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An edge-triggered flip-flop is a de facto standard sequencing element in ASIC designs. As sequencing elements occupy increasing portion of timing and power, it is necessary to explore other types of elements. We identify pulsed-latch and dual edge-triggered flip-flop as two promising candidates. The challenges when they are employed for conventional ASIC design are identified, and potential solutions are addressed.
Publisher
IEEE
Issue Date
2011-08-09
Language
English
Citation

The 54th IEEE Ineternational Midwest Symposium on Circuits and Systems (MWSCAS), pp.394 - 397

URI
http://hdl.handle.net/10203/172497
Appears in Collection
EE-Conference Papers(학술회의논문)

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