DC Field | Value | Language |
---|---|---|
dc.contributor.author | Paik, Seungwhun | - |
dc.contributor.author | Kung, Jaeha | - |
dc.contributor.author | Shin, Youngsoo | - |
dc.date.accessioned | 2013-03-29T17:30:11Z | - |
dc.date.available | 2013-03-29T17:30:11Z | - |
dc.date.created | 2012-11-30 | - |
dc.date.issued | 2011-08-09 | - |
dc.identifier.citation | The 54th IEEE Ineternational Midwest Symposium on Circuits and Systems (MWSCAS), pp.394 - 397 | - |
dc.identifier.uri | http://hdl.handle.net/10203/172497 | - |
dc.description.abstract | An edge-triggered flip-flop is a de facto standard sequencing element in ASIC designs. As sequencing elements occupy increasing portion of timing and power, it is necessary to explore other types of elements. We identify pulsed-latch and dual edge-triggered flip-flop as two promising candidates. The challenges when they are employed for conventional ASIC design are identified, and potential solutions are addressed. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | Exploring the Opportunity of Optimizing Sequencing Elements in ASIC Designs | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 394 | - |
dc.citation.endingpage | 397 | - |
dc.citation.publicationname | The 54th IEEE Ineternational Midwest Symposium on Circuits and Systems (MWSCAS) | - |
dc.identifier.conferencecountry | KO | - |
dc.identifier.conferencelocation | Seoul | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.contributor.nonIdAuthor | Paik, Seungwhun | - |
dc.contributor.nonIdAuthor | Kung, Jaeha | - |
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