Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor

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Balancing the execution times of concurrent tasks in a multi-core processor is critical to achieving good performance scaling with increasing core count. However, this is difficult when the tasks' execution times are not known in advance. In this work, we propose an intelligent Network-on-Chip that performs bandwidth regulation using weighted round robin packet arbitration to balance the execution times of 4 Feature Extraction Clusters whose workloads vary depending on the input content. A neuro-fuzzy inference block, named the Intelligent Inference Engine, predicts the workload of each FEC, and assigns a priority weight to each FEC channel. As a result, 34% reduction in synchronization overhead due to unbalanced execution time was achieved, and the overall execution time was reduced by 11.5%.
Publisher
Institute of Electrical and Electronics Engineers Inc.
Issue Date
2010-09-19
Language
English
Citation

32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010

ISSN
0886-5930
URI
http://hdl.handle.net/10203/164918
Appears in Collection
EE-Conference Papers(학술회의논문)
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