Integration of Dual Metal Gate/High-K dielectric Stacks for Fermi-Level Pinning FreeIntegration of Dual Metal Gate/High-K dielectric Stacks for Fermi-Level Pinning Free
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Cho, Byung Jin | - |
| dc.date.accessioned | 2013-03-18T00:50:11Z | - |
| dc.date.available | 2013-03-18T00:50:11Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2005-06-02 | - |
| dc.identifier.citation | The 2nd International Workshop on Nanoscale Semiconductor Devices, v., no., pp.253 - 279 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/143322 | - |
| dc.language | ENG | - |
| dc.title | Integration of Dual Metal Gate/High-K dielectric Stacks for Fermi-Level Pinning Free | - |
| dc.title.alternative | Integration of Dual Metal Gate/High-K dielectric Stacks for Fermi-Level Pinning Free | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.beginningpage | 253 | - |
| dc.citation.endingpage | 279 | - |
| dc.citation.publicationname | The 2nd International Workshop on Nanoscale Semiconductor Devices | - |
| dc.identifier.conferencecountry | South Korea | - |
| dc.identifier.conferencecountry | South Korea | - |
| dc.contributor.localauthor | Cho, Byung Jin | - |
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