DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yu, S | ko |
dc.contributor.author | Petranovic, DM | ko |
dc.contributor.author | Krishnan, S | ko |
dc.contributor.author | Lee, Kwyro | ko |
dc.contributor.author | Yang, CY | ko |
dc.date.accessioned | 2009-11-25T01:01:24Z | - |
dc.date.available | 2009-11-25T01:01:24Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2006-01 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.53, pp.135 - 145 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/13282 | - |
dc.description.abstract | An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 mu m CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CROSSTALK | - |
dc.subject | EXPRESSIONS | - |
dc.subject | DESIGN | - |
dc.title | Loop-based inductance extraction and modeling for multiconductor on-chip interconnects | - |
dc.type | Article | - |
dc.identifier.wosid | 000234306700021 | - |
dc.identifier.scopusid | 2-s2.0-33748312331 | - |
dc.type.rims | ART | - |
dc.citation.volume | 53 | - |
dc.citation.beginningpage | 135 | - |
dc.citation.endingpage | 145 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/TED.2005.860655 | - |
dc.contributor.localauthor | Lee, Kwyro | - |
dc.contributor.nonIdAuthor | Yu, S | - |
dc.contributor.nonIdAuthor | Petranovic, DM | - |
dc.contributor.nonIdAuthor | Krishnan, S | - |
dc.contributor.nonIdAuthor | Yang, CY | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | electromagnetic coupling | - |
dc.subject.keywordAuthor | inductance | - |
dc.subject.keywordAuthor | integrated circuit interconnections | - |
dc.subject.keywordAuthor | modeling | - |
dc.subject.keywordPlus | CROSSTALK | - |
dc.subject.keywordPlus | EXPRESSIONS | - |
dc.subject.keywordPlus | DESIGN | - |
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