DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Kwang-Il | - |
dc.contributor.author | Kim, Lee-Sup | - |
dc.contributor.author | Park, Kwang-Il | - |
dc.contributor.author | Jun, Young-Hyun | - |
dc.contributor.author | Kim, Kinam | - |
dc.date.accessioned | 2009-09-22T01:04:17Z | - |
dc.date.available | 2009-09-22T01:04:17Z | - |
dc.date.issued | 2008-09 | - |
dc.identifier.citation | IEE Electronics Letters, Vol. 44, No. 19 | en |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/11422 | - |
dc.description.abstract | A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18um CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4ps, respectively. The power consumption of the DLL is 12mW from a 1.8V supply voltage. | en |
dc.language.iso | en_US | en |
dc.publisher | IEEE | en |
dc.title | Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface | en |
dc.type | Article | en |
dc.identifier.doi | 10.1049/el:20081833 | - |
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