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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

A time-interleaved flash-SAR architecture for high speed A/D conversion

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dc.contributor.authorSung, B.R.S.-
dc.contributor.authorCho, S.-H.-
dc.contributor.authorLee, C.-K.-
dc.contributor.authorKim, J.-I.-
dc.contributor.authorRyu, Seung-Tak-
dc.date.accessioned2009-08-24-
dc.date.available2009-08-24-
dc.date.created2012-02-06-
dc.date.issued2009-05-24-
dc.identifier.citation2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, v., no., pp.984 - 987-
dc.identifier.issn0271-4310-
dc.identifier.urihttp://hdl.handle.net/10203/10679-
dc.description.sponsorshipThis work was supported by the Korea Science and Engineering Foundation (KOSEF) grant funded by the Korea government (MEST) (No. R11-2005-209-06002-0). The CAD tools have been supported by IDEC of KAIST.en
dc.languageENG-
dc.language.isoen_USen
dc.publisherIEEE-
dc.titleA time-interleaved flash-SAR architecture for high speed A/D conversion-
dc.typeConference-
dc.identifier.scopusid2-s2.0-70350166452-
dc.type.rimsCONF-
dc.citation.beginningpage984-
dc.citation.endingpage987-
dc.citation.publicationname2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009-
dc.identifier.conferencecountryTaiwan, Province of China-
dc.identifier.conferencecountryTaiwan, Province of China-
dc.contributor.localauthorRyu, Seung-Tak-
dc.contributor.nonIdAuthorSung, B.R.S.-
dc.contributor.nonIdAuthorCho, S.-H.-
dc.contributor.nonIdAuthorLee, C.-K.-
dc.contributor.nonIdAuthorKim, J.-I.-
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EE-Conference Papers(학술회의논문)
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