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Showing results 42 to 46 of 46

42
TEPS: Transient error protection utilizing sub-word parallelism

Hong, Seokin; Kim, Soontae, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp.286 - 291, 2009-05-14

43
Ternary Cache: Three-valued MLC STT-RAM Caches

Hong, Seokin; Lee, Jongmin; Kim, Soontae, IEEE International Conference on Computer Design, IEEE Circuits and Systems Society, 2014-10-20

44
TLB Index-based Tagging for Cache Energy Reduction

Lee, Jongmin; Hong, Seokin; Kim, Soontae, ACM/IEEE International Symposium on Low Power Electronics and Design, pp.85 - 90, IEEE-CAS and ACM-SIGDA, 2011-08-01

45
Use of local memory for efficient Java execution

Tomar, S.; Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., IEEE International Conference on Computer Design, pp.468 - 473, 2001-09

46
Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system

Kim, Soontae; Lee, Jongmin, 20th Great Lakes Symposium on VLSI, GLSVLSI 2010, pp.257 - 262, 2010-05-16

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