Showing results 38 to 46 of 46
Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD Performance Moon, Junoh; Kang, Mincheol; Lee, Wonyoung; Kim, Soontae, 25th Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.576 - 579, IEEE, 2022-03 |
Scheduling Reusable Instructions for Power Reduction Hu, J.S.; Vijaykrishnan, N.; Kim, Soontae; Kandemir, M.; Irwin, M.J., Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004. , v.1, pp.148 - 153, 2004-02 |
SimTag: Exploiting tag bits similarity to improve the reliability of the data caches Kim, Jesung; Kim, Soontae; Lee, Yebin, Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, pp.941 - 944, 2010-03-08 |
Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power Lee, Yebin; Kim, Soontae; Hong, Seokin; Lee, Jongmin, IEEE International Symposium on High Performance Computer Architecture , pp.25 - 34, IEEE Computer Society, 2013-02-23 |
TEPS: Transient error protection utilizing sub-word parallelism Hong, Seokin; Kim, Soontae, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp.286 - 291, 2009-05-14 |
Ternary Cache: Three-valued MLC STT-RAM Caches Hong, Seokin; Lee, Jongmin; Kim, Soontae, IEEE International Conference on Computer Design, IEEE Circuits and Systems Society, 2014-10-20 |
TLB Index-based Tagging for Cache Energy Reduction Lee, Jongmin; Hong, Seokin; Kim, Soontae, ACM/IEEE International Symposium on Low Power Electronics and Design, pp.85 - 90, IEEE-CAS and ACM-SIGDA, 2011-08-01 |
Use of local memory for efficient Java execution Tomar, S.; Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., IEEE International Conference on Computer Design, pp.468 - 473, 2001-09 |
Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system Kim, Soontae; Lee, Jongmin, 20th Great Lakes Symposium on VLSI, GLSVLSI 2010, pp.257 - 262, 2010-05-16 |
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