Showing results 27 to 46 of 46
Near-Threshold Voltage Scaling in Last level Caches Tayyeb Mahmood; Kim, Soontae, International Exposition Yeosu Korea, International Conference on Information Technology (YSEC 2012), 한국정보처리학회, 2012-04-27 |
Network delay-aware energy management for mobile systems Ju, Minho; Kim, Hyeonggyu; Kim, Soontae, Design, Automation & Test in Europe Conference & Exhibition, European Design and Automation Association (EDAA), 2016-03-14 |
On Load Latency in Low-Power Caches Kim, Soontae; Vijaykrishnan, N.; Irwin, M.J.; John, L.K., Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. (ISLPED '03) , pp.258 - 261, 2003-08-01 |
PAPA: Partial Page-aware Page Allocation in TLC Flash SSD for Performance Enhancement Imran, Fareed; Kang, Mincheol; Lee, Wonyoung; Kim, Soontae, 36th International Conference on Massive Storage Systems and Technology, MSST 2020, Santa Clara University, 2020-10-29 |
Partial Row Activation for Low-Power DRAM System Lee, Yebin; Kim, Hyeonggyu; Hong, Seokin; Kim, Soontae, IEEE International Symposium on High Performance Computer Architecture, pp.217 - 228, IEEE Computer Society, 2017-02-06 |
Performance Controllable Shared Cache Architecture for Multi-Core Soft Real-Time Systems Lee, Myoungjun; Kim, Soontae, IEEE International Conference on Computer Design, pp.519 - 522, IEEE, 2013-10-07 |
Performance modeling using hardware performance counters Kim, Soontae, Triangle Symposium on Advanced ICT, 2010-01-25 |
Power-aware Partitioned Cache Architectures Kim, Soontae; Kandemir, M.; Sivasubramaniam, A.; Irwin, M.J.; Geethanjali, E., ACM/IEEE International Symposium on Low Power Electronics and Design, pp.64 - 67, 2001-08 |
Predictive Precharging for Bitline Leakage Energy Reduction Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., 15th Annual IEEE International ASIC/SOC Conference, 2002. , pp.36 - 40, 2002-09 |
Reducing ALU and Register File Energy by Dynamic Zero Detection Kim, Soontae, International Performance Computing and Communication Conference, pp.365 - 371, IEEE Internationa Performance, Computing, and Communications Conference, 2007. (IPCCC 2007), 2007-04 |
Resuscitating Privacy-Preserving Mobile Payment with Customer in Complete Control Konidala, Divyan M.; Dwijaksara, Made H; Kim, Kwangjo; Lee, Dongman; Lee, Byoungcheon; Kim, Daeyoung; Kim, Soontae, International Workshop on Smartphone Applications and Services, 2010-12-09 |
Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD Performance Moon, Junoh; Kang, Mincheol; Lee, Wonyoung; Kim, Soontae, 25th Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.576 - 579, IEEE, 2022-03 |
Scheduling Reusable Instructions for Power Reduction Hu, J.S.; Vijaykrishnan, N.; Kim, Soontae; Kandemir, M.; Irwin, M.J., Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004. , v.1, pp.148 - 153, 2004-02 |
SimTag: Exploiting tag bits similarity to improve the reliability of the data caches Kim, Jesung; Kim, Soontae; Lee, Yebin, Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, pp.941 - 944, 2010-03-08 |
Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power Lee, Yebin; Kim, Soontae; Hong, Seokin; Lee, Jongmin, IEEE International Symposium on High Performance Computer Architecture , pp.25 - 34, IEEE Computer Society, 2013-02-23 |
TEPS: Transient error protection utilizing sub-word parallelism Hong, Seokin; Kim, Soontae, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp.286 - 291, 2009-05-14 |
Ternary Cache: Three-valued MLC STT-RAM Caches Hong, Seokin; Lee, Jongmin; Kim, Soontae, IEEE International Conference on Computer Design, IEEE Circuits and Systems Society, 2014-10-20 |
TLB Index-based Tagging for Cache Energy Reduction Lee, Jongmin; Hong, Seokin; Kim, Soontae, ACM/IEEE International Symposium on Low Power Electronics and Design, pp.85 - 90, IEEE-CAS and ACM-SIGDA, 2011-08-01 |
Use of local memory for efficient Java execution Tomar, S.; Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., IEEE International Conference on Computer Design, pp.468 - 473, 2001-09 |
Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system Kim, Soontae; Lee, Jongmin, 20th Great Lakes Symposium on VLSI, GLSVLSI 2010, pp.257 - 262, 2010-05-16 |
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