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A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock Yang, Isaak; Cho, Kwang-Hyun, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.29, no.3, pp.512 - 518, 2021-03 |
Timing error masking by exploiting operand value locality in SIMD architecture = SIMD 구조의 피연산자 값 지역성을 활용한 타이밍 오류 제거 기법link Sim, Jaehyeong; 심재형; et al, 한국과학기술원, 2014 |
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