Timing error masking by exploiting operand value locality in SIMD architecture

Abstract

A significant energy is consumed by the voltage guardband to ensure correct operations in modern processors even under the rarely occurring worst-case conditions. Furthermore, worsening PVT variation is making the voltage guardband grow. This bounded voltage scaling trend conflicts with the strong need for low-power, low-energy solutions arise from ever tightening power budget and dark silicon issue. Consequently, better-than-worst-case design is becoming a promising solution as it achieves a significant amount of energy savings by removing the voltage guardband and scaling the supply voltage additionally. In order to guarantee correct operations of a processor in the better-than-worst-case-design, Razor flip-flops and Instruction Replay are widely used to detect and correct timing errors induced by voltage over-scaling. However, the potential gain from scaling the supply voltage is limited as error rate and the following occurrence of Instruction Replay increase. Moreover, throughput and energy loss caused by replaying the pipeline is a critical problem in SIMD architecture. In this work, an error masking scheme targeted for integer additions in SIMD architecture is proposed. The masking is done by applying the concept of partial reuse to potential erroneous instructions. Two critical observations are conducted in order for the reuse and mask scheme to work properly: temporal operand value locality and operand value locality across SIMD lanes. Simulation results based on the real operands sampled from 15 CUDA benchmarks strongly prove that both temporal operand value locality and operand value locality across lanes exist in SIMD architecture. In addition, detailed implementations for reuse and mask are proposed in this work. Masking logic is inserted to integer ALUs of each SIMD lanes. A single reuse table is implemented for an entire SIMD processor, and it is accessible before and after the execution stage. Intensive simulations on 15 CUDA benchmarks were performed to evaluate our proposed implementation. 10 design variants of our scheme are analyzed to get an optimal solution. Our result show that a significant amount timing errors are masked by the proposed design. Also, throughput comparable to that of error-free execution is achieved, which is a crucial benefit for throughput-oriented SIMD architecture. Finally, our scheme obtains up to 5.1% improvement in energy consumption and 30% improvement in EDP when compared to energy optimal point of Razor only design.