A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache

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dc.contributor.authorYoon, Jae-Sungko
dc.contributor.authorYu, Chang-Hyoko
dc.contributor.authorKim, Dong-Hyunko
dc.contributor.authorKim, Lee-Supko
dc.date.accessioned2013-03-11T17:55:31Z-
dc.date.available2013-03-11T17:55:31Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2011-04-
dc.identifier.citationIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.4, pp.525 - 537-
dc.identifier.issn1063-8210-
dc.identifier.urihttp://hdl.handle.net/10203/99797-
dc.description.abstractThis paper presents a fully programmable 3-D graphics processor using unified shaders for mobile environment. In the system level, we adopted dual-core, dual-issue VLIW, and multithreading methods to utilize instruction, data, and task level parallelism in the graphics applications. In the shader core level, a novel IEEE-754 compliant 4-D vector inner product arithmetic unit and a configurable texture cache are proposed. Using these methods, the proposed processor achieves 143 Mvertices/s and 2.3 Gtexels/s consuming the power of 367 mW. The evaluation shows significant performance and power-delay product benefits. For real graphics applications, test results indicate 2.07 times improvement in performance and 34% reduction in power-delay product compared to previous mobile 3-D graphics processors. The proposed 3-D graphics processor is implemented in 4.5 x 4.5 mm using 0.18-mu m CMOS technology.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectMOBILE APPLICATIONS-
dc.subjectVERTEX PROCESSOR-
dc.subjectARCHITECTURE-
dc.subjectSYSTEMS-
dc.subjectSOC-
dc.titleA Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache-
dc.typeArticle-
dc.identifier.wosid000288681400001-
dc.identifier.scopusid2-s2.0-79953081001-
dc.type.rimsART-
dc.citation.volume19-
dc.citation.issue4-
dc.citation.beginningpage525-
dc.citation.endingpage537-
dc.citation.publicationnameIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS-
dc.contributor.localauthorKim, Lee-Sup-
dc.contributor.nonIdAuthorYu, Chang-Hyo-
dc.contributor.nonIdAuthorKim, Dong-Hyun-
dc.type.journalArticleArticle-
dc.subject.keywordAuthor3-D graphics-
dc.subject.keywordAuthorconfigurable cache-
dc.subject.keywordAuthorunified shader-
dc.subject.keywordAuthorvector inner product-
dc.subject.keywordAuthorVLIW-
dc.subject.keywordPlusMOBILE APPLICATIONS-
dc.subject.keywordPlusVERTEX PROCESSOR-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusSYSTEMS-
dc.subject.keywordPlusSOC-
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