HLS-1: A High-Level Synthesis Framework for Latch-Based Architectures

Abstract

Level-sensitive latches are widely used in high-performance custom designs while edge-triggered. flip-flops are predominantly used in application-specific integrated circuits. We consider a latch as a basis for storage and address each step of high-level synthesis (HLS), including scheduling, allocation, and control synthesis. While the use of latches provides an opportunity to reduce the latency during the scheduling, the register allocation has to take extra conflicts caused by latch into account, and the control synthesis has to be tailored to support the latch-based data-path. Optimization potentials specific to this HLS are identified and solutions are proposed. Specifically, the register allocation can be improved by re. ning the operation schedule in a way to reduce the number of edges in a register conflict graph; the latency can be reduced by adjusting the clock duty cycle in a way to generate a tighter schedule. All the steps of HLS and optimization procedures were integrated into a framework called HLS-1. It was tested on benchmark designs implemented in 1.1-V, 45 nm complementary metal-oxide-semiconductor technology. Compared to the conventional HLS, HLS-1 was able to reduce the latency by 18.2% on average with 9.2% less area and 16.0% less power consumption. The application of HLS-1 to an industrial example is demonstrated through the design of a module extracted from H.264/advanced video coding.