DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Youngsoo | ko |
dc.contributor.author | Chae, SI | ko |
dc.contributor.author | Choi, K | ko |
dc.date.accessioned | 2007-08-07T06:31:37Z | - |
dc.date.available | 2007-08-07T06:31:37Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-04 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.9, no.2, pp.377 - 383 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/979 | - |
dc.description.abstract | This paper presents two bus coding schemes for power optimization of application-specific systems: Partial Bus-invert coding and its extension to Multiway Partial Bus-invert coding. In the first scheme, only a selected subgroup of bus lines is encoded to avoid unnecessary inversion of relatively inactive and/or uncorrelated bus lines which are not included in the subgroup. In the extended scheme, we partition a bus into multiple subbuses by clustering highly correlated bus lines and then encode each subbus independently. We describe a heuristic algorithm of partitioning a bus into subbuses for each encoding scheme. Experimental results for various examples indicate that both encoding schemes are highly efficient for application-specific systems. | - |
dc.description.sponsorship | This work was supported in part by the Korea Research Foundation under a Nondirected Research Fund. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | ADDRESS | - |
dc.title | Partial bus-invert coding for power optimization of application-specific systems | - |
dc.type | Article | - |
dc.identifier.wosid | 000169035300013 | - |
dc.identifier.scopusid | 2-s2.0-0035301452 | - |
dc.type.rims | ART | - |
dc.citation.volume | 9 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 377 | - |
dc.citation.endingpage | 383 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.contributor.nonIdAuthor | Chae, SI | - |
dc.contributor.nonIdAuthor | Choi, K | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | digital complementary metal-oxide-semiconductor (CMOS | - |
dc.subject.keywordAuthor | low-power dissipation | - |
dc.subject.keywordAuthor | memory | - |
dc.subject.keywordAuthor | switching activity | - |
dc.subject.keywordAuthor | system level | - |
dc.subject.keywordAuthor | tradeoffs | - |
dc.subject.keywordPlus | ADDRESS | - |
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