DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Sunwoo | ko |
dc.contributor.author | Lim, Jae-Sung | ko |
dc.contributor.author | Baik, Seung Jae | ko |
dc.date.accessioned | 2013-03-09T08:21:07Z | - |
dc.date.available | 2013-03-09T08:21:07Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2011 | - |
dc.identifier.citation | JOURNAL OF THE ELECTROCHEMICAL SOCIETY, v.158, no.11, pp.K193 - K196 | - |
dc.identifier.issn | 0013-4651 | - |
dc.identifier.uri | http://hdl.handle.net/10203/95850 | - |
dc.description.abstract | We report the latest works on via interconnects of future memory or LSI devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. MWCNTs are grown vertically in 80 nm via holes using plasma-enhanced chemical vapor deposition. The carbon nanotube (CNT) via interconnects are integrated into an 8-inch Si wafer in full compatibility with conventional semiconductor processes. We have used buried catalyst method for the catalyst layer deposition, two-step etch method for achieving via etch stop on the thin catalyst layer (ca. 3 nm), and the chemical mechanical polishing (CMP) process for cutting CNT. The two-step etch method is composed of two consecutive etch steps: the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to relieve the damage of the catalyst layer. After a full integration, a resistance of 293 similar to 493 Omega and a CNT density of about 4 x 10(11)/cm(2) have been achieved for the 80 nm via. These results show that the 2-step etch scheme is a promising candidate for the realization of CNT interconnects in conventional semiconductor devices. (C) 2011 The Electrochemical Society. [DOI: 10.1149/2.018111jes] All rights reserved. | - |
dc.language | English | - |
dc.publisher | Electrochemical Soc Inc | - |
dc.subject | GROWTH | - |
dc.subject | TRANSPORT | - |
dc.subject | DIAMETER | - |
dc.subject | METAL | - |
dc.subject | TI | - |
dc.title | Integration of Carbon Nanotube Interconnects for Full Compatibility with Semiconductor Technologies | - |
dc.type | Article | - |
dc.identifier.wosid | 000295626000080 | - |
dc.identifier.scopusid | 2-s2.0-80054011429 | - |
dc.type.rims | ART | - |
dc.citation.volume | 158 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | K193 | - |
dc.citation.endingpage | K196 | - |
dc.citation.publicationname | JOURNAL OF THE ELECTROCHEMICAL SOCIETY | - |
dc.contributor.nonIdAuthor | Lee, Sunwoo | - |
dc.contributor.nonIdAuthor | Lim, Jae-Sung | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | GROWTH | - |
dc.subject.keywordPlus | TRANSPORT | - |
dc.subject.keywordPlus | DIAMETER | - |
dc.subject.keywordPlus | METAL | - |
dc.subject.keywordPlus | TI | - |
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