DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, S. -H. | ko |
dc.contributor.author | Lee, H. -D. | ko |
dc.contributor.author | Kim, K. -D. | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.contributor.author | Kwon, J. -K. | ko |
dc.date.accessioned | 2013-03-09T06:12:36Z | - |
dc.date.available | 2013-03-09T06:12:36Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010-03 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.46, no.5, pp.335 - 4853 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/95561 | - |
dc.description.abstract | A new topology in PLL architecture dual-mode K(VCO) (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65 nm CMOS and shows about 3 ps RMS jitter, phase noise of -107 and -109 dBc/Hz at 100 kHz, 1 MHz offset frequency and reference spur of 68.5 dBc. | - |
dc.language | English | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.title | Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000275830400014 | - |
dc.identifier.scopusid | 2-s2.0-77949353317 | - |
dc.type.rims | ART | - |
dc.citation.volume | 46 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 335 | - |
dc.citation.endingpage | 4853 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.identifier.doi | 10.1049/el.2010.3553 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Cho, S. -H. | - |
dc.contributor.nonIdAuthor | Lee, H. -D. | - |
dc.contributor.nonIdAuthor | Kim, K. -D. | - |
dc.contributor.nonIdAuthor | Kwon, J. -K. | - |
dc.type.journalArticle | Article | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.