DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Jaehyun | ko |
dc.contributor.author | Oh, Chungki | ko |
dc.contributor.author | Shin, Youngsoo | ko |
dc.date.accessioned | 2013-03-09T01:49:56Z | - |
dc.date.available | 2013-03-09T01:49:56Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2009-12 | - |
dc.identifier.citation | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.15, no.1 | - |
dc.identifier.issn | 1084-4309 | - |
dc.identifier.uri | http://hdl.handle.net/10203/95031 | - |
dc.description.abstract | The current use of multi-V-t to control leakage power targets combinational gates, even though sequential elements such as flip-flops and latches also contribute appreciable leakage. We can, nevertheless, apply multi-V-t to flip-flops, but few can take advantage of high-V-t, which causes abrupt changes in timing. We combine low-and high-V-t at the transistor level to design mixed-V-t flip-flops with reduced leakage, an unchanged footprint, and a small increase in either setup time or clock-to-Q delay, but not both. An allocation algorithm for two V(t)s determines the V-t (mixed, high, or low) of each flip-flop and the V-t of each combinational gate (high or low) in a sequential circuit. Experiments with 65-nm technology show an average leakage saving of 42% compared to conventional multi-V-t approaches; the leakage of flip-flops alone is cut by 78%. This saving is largely unaffected by die-to-die or within-die process variations, which we show through simulations. Standard deviation of leakage caused by process variation is also reduced due to less use of low-V-t devices. We also extend our approach to three V(t)s, and obtain a further 14% reduction in leakage. | - |
dc.language | English | - |
dc.publisher | ASSOC COMPUTING MACHINERY | - |
dc.title | Minimizing Leakage Power of Sequential Circuits through Mixed-V-t Flip-Flops and Multi-V-t Combinational Gates | - |
dc.type | Article | - |
dc.identifier.wosid | 000273323600004 | - |
dc.identifier.scopusid | 2-s2.0-74049093998 | - |
dc.type.rims | ART | - |
dc.citation.volume | 15 | - |
dc.citation.issue | 1 | - |
dc.citation.publicationname | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | - |
dc.identifier.doi | 10.1145/1640457.1640461 | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Algorithms | - |
dc.subject.keywordAuthor | Design | - |
dc.subject.keywordAuthor | Flip-flop | - |
dc.subject.keywordAuthor | leakage current | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | mixed-V-t | - |
dc.subject.keywordAuthor | sequential circuit | - |
dc.subject.keywordPlus | VOLTAGE | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | SCHEME | - |
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