DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Kwang-Il | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.contributor.author | Park, Kwang-Il | ko |
dc.contributor.author | Jun, Young-Hyun | ko |
dc.contributor.author | Choi, Joo Sun | ko |
dc.contributor.author | Kim, Kinam | ko |
dc.date.accessioned | 2013-03-09T01:30:16Z | - |
dc.date.available | 2013-03-09T01:30:16Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2009-08 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.44, pp.2222 - 2232 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/94982 | - |
dc.description.abstract | A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mu m CMOS process and operates at 5 Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The peak-to-peak jitter of output data is 52.82 ps | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | EQUALIZATION | - |
dc.subject | CANCELLATION | - |
dc.title | A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme | - |
dc.type | Article | - |
dc.identifier.wosid | 000268337800012 | - |
dc.identifier.scopusid | 2-s2.0-68549098047 | - |
dc.type.rims | ART | - |
dc.citation.volume | 44 | - |
dc.citation.beginningpage | 2222 | - |
dc.citation.endingpage | 2232 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2009.2022303 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Oh, Kwang-Il | - |
dc.contributor.nonIdAuthor | Park, Kwang-Il | - |
dc.contributor.nonIdAuthor | Jun, Young-Hyun | - |
dc.contributor.nonIdAuthor | Choi, Joo Sun | - |
dc.contributor.nonIdAuthor | Kim, Kinam | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | crosstalk | - |
dc.subject.keywordAuthor | DDR | - |
dc.subject.keywordAuthor | glitch | - |
dc.subject.keywordAuthor | memory interface | - |
dc.subject.keywordAuthor | signal integrity | - |
dc.subject.keywordAuthor | staggered bus | - |
dc.subject.keywordAuthor | transceiver | - |
dc.subject.keywordPlus | EQUALIZATION | - |
dc.subject.keywordPlus | CANCELLATION | - |
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