DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoo, Junbeom | ko |
dc.contributor.author | Cha, Sungdeok | ko |
dc.contributor.author | Jee, Eunk Young | ko |
dc.date.accessioned | 2013-03-08T16:27:43Z | - |
dc.date.available | 2013-03-08T16:27:43Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2009-02 | - |
dc.identifier.citation | NUCLEAR ENGINEERING AND TECHNOLOGY, v.41, no.1, pp.79 - 90 | - |
dc.identifier.issn | 1738-5733 | - |
dc.identifier.uri | http://hdl.handle.net/10203/93568 | - |
dc.description.abstract | Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design. | - |
dc.language | English | - |
dc.publisher | KOREAN NUCLEAR SOC | - |
dc.subject | SPECIFICATION | - |
dc.subject | SYSTEMS | - |
dc.subject | DESIGN | - |
dc.title | VERIFICATION OF PLC PROGRAMS WRITTEN IN FBD WITH VIS | - |
dc.type | Article | - |
dc.identifier.wosid | 000264223300008 | - |
dc.identifier.scopusid | 2-s2.0-62249114181 | - |
dc.type.rims | ART | - |
dc.citation.volume | 41 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 79 | - |
dc.citation.endingpage | 90 | - |
dc.citation.publicationname | NUCLEAR ENGINEERING AND TECHNOLOGY | - |
dc.contributor.nonIdAuthor | Yoo, Junbeom | - |
dc.contributor.nonIdAuthor | Cha, Sungdeok | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Verification | - |
dc.subject.keywordAuthor | Equivalence Checking | - |
dc.subject.keywordAuthor | VIS | - |
dc.subject.keywordAuthor | Verilog | - |
dc.subject.keywordAuthor | Function Block Diagram | - |
dc.subject.keywordAuthor | Programmable Logic Controller | - |
dc.subject.keywordAuthor | IEC-61131 | - |
dc.subject.keywordPlus | SPECIFICATION | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordPlus | DESIGN | - |
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