DC Field | Value | Language |
---|---|---|
dc.contributor.author | Xie, Ningde | ko |
dc.contributor.author | Xu, Wei | ko |
dc.contributor.author | Zhang, Tong | ko |
dc.contributor.author | Haratsch, Erich F. | ko |
dc.contributor.author | Moon, Jaekyun | ko |
dc.date.accessioned | 2013-03-07T20:26:43Z | - |
dc.date.available | 2013-03-07T20:26:43Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2008-12 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON MAGNETICS, v.44, no.12, pp.4784 - 4789 | - |
dc.identifier.issn | 0018-9464 | - |
dc.identifier.uri | http://hdl.handle.net/10203/91234 | - |
dc.description.abstract | In this paper, we examine the potential of applying concatenated low-density parity-check (LDPC) and Bose-Chaudhuri-Hocquenghem (BCH) coding for magnetic recording read channel with a 4 kB sector format. One key observation for such concatenated coding systems is that the overall error correction capability can be improved by exploiting the iteration-by-iteration bit error number oscillation behavior in case of inner LDPC code decoding failures. Moreover, assisted by field programmable gate array (FPGA)-based simulation platforms, empirical error-correcting performance analysis can reach a very low sector error rate (e.g., 10(-10) and below), which is almost infeasible for LDPC-only coding systems. Finally, concatenated coding can further reduce the silicon cost. By implementing a high-speed FPGA-based perpendicular recording read channel simulator, we investigate a 4 kB rate-15/16 concatenated coding system with a 512-byte rate-19/20 inner LDPC code and an outer 4 kB BCH code. We apply a decoding strategy that can fully utilize the bit error number oscillation behavior of inner LDPC code decoding, and show that its sector error rate drops down to 10(-11). For the purpose of comparison, we use the FPGA-based simulator to empirically observe the performance of 4 kB rate-15/16 LDPC and Reed-Solomon (RS) codes down to 10(-7)-10(-8). Finally, we estimate the silicon cost of this concatenated coding system at 65 nm node, and compare it with that of the RS-only and LDPC-only coding systems. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CODES | - |
dc.subject | DESIGN | - |
dc.subject | DECODER | - |
dc.title | Concatenated Low-Density Parity-Check and BCH Coding System for Magnetic Recording Read Channel With 4 kB Sector Format | - |
dc.type | Article | - |
dc.identifier.wosid | 000262556800029 | - |
dc.identifier.scopusid | 2-s2.0-77952865538 | - |
dc.type.rims | ART | - |
dc.citation.volume | 44 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 4784 | - |
dc.citation.endingpage | 4789 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON MAGNETICS | - |
dc.identifier.doi | 10.1109/TMAG.2008.2004380 | - |
dc.contributor.localauthor | Moon, Jaekyun | - |
dc.contributor.nonIdAuthor | Xie, Ningde | - |
dc.contributor.nonIdAuthor | Xu, Wei | - |
dc.contributor.nonIdAuthor | Zhang, Tong | - |
dc.contributor.nonIdAuthor | Haratsch, Erich F. | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Application-specific integrated circuit (ASIC) | - |
dc.subject.keywordAuthor | BCH | - |
dc.subject.keywordAuthor | concatenated | - |
dc.subject.keywordAuthor | field programmable gate array (FPGA) | - |
dc.subject.keywordAuthor | low-density parity-check (LDPC) | - |
dc.subject.keywordPlus | CODES | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | DECODER | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.