A new fast cell resequence mechanism for multipath ATM switches

Abstract

A new cell resequence mechanism is proposed to restore the cell sequence in multipath ATM switches. Since the proposed mechanism uses per-VC logical queues which store only the cells belonging to the same VC, the mechanism can reduce processing time compared to conventional resequence mechanisms. The mechanism also has no limitation on the peak rate of VC's and needs no arbitration function to select an output cell, The mechanism can be implemented using a RAM buffer, a content addressable memory/random access memory (CAM/RAM) table, a controller, etc.