DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.contributor.author | Kim, Kuk-Hwan | ko |
dc.contributor.author | Han, Jin-Woo | ko |
dc.contributor.author | Ryu, Seong-Wan | ko |
dc.contributor.author | Lee, Hyunjin | ko |
dc.date.accessioned | 2013-03-06T21:10:58Z | - |
dc.date.available | 2013-03-06T21:10:58Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2007-11 | - |
dc.identifier.citation | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.7, no.11, pp.4126 - 4130 | - |
dc.identifier.issn | 1533-4880 | - |
dc.identifier.uri | http://hdl.handle.net/10203/88473 | - |
dc.description.abstract | In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time. | - |
dc.language | English | - |
dc.publisher | AMER SCIENTIFIC PUBLISHERS | - |
dc.subject | SUBSTRATE CURRENT MODEL | - |
dc.title | Extremely scaled 3-dimensional multiple-gate technologies for terabit era | - |
dc.type | Article | - |
dc.identifier.wosid | 000250576500097 | - |
dc.type.rims | ART | - |
dc.citation.volume | 7 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 4126 | - |
dc.citation.endingpage | 4130 | - |
dc.citation.publicationname | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Kim, Kuk-Hwan | - |
dc.contributor.nonIdAuthor | Han, Jin-Woo | - |
dc.contributor.nonIdAuthor | Ryu, Seong-Wan | - |
dc.contributor.nonIdAuthor | Lee, Hyunjin | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | all-around gate | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | punchthrough | - |
dc.subject.keywordAuthor | series resistance | - |
dc.subject.keywordAuthor | gate misalignment | - |
dc.subject.keywordAuthor | hot-carrier injection | - |
dc.subject.keywordPlus | SUBSTRATE CURRENT MODEL | - |
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