Effects of electroplating parameters on the defects of copper via for 3D SiP

Abstract

Electroplating of copper in via filling is very important in 3D SiP (System in Packaging). Defect free via filling can be obtained through additive in the electrolyte and current type control. Via in Si wafer were formed by RIE method with 170 μm depth and 50 μm in diameter. Seed layers were deposited by ionized metal plasma (IMP) sputtering; Ta for diffusion barrier, Cu for conductive layer. Via was filled with copper by electroplating method. Different types of additives were used in via filling; PEG, SPS, Cl and JGB. Defects in via were controlled and eliminated by precise monitoring of additive concentration and input current. The optimum condition of electroplating was determined by getting cross-sectional images of filled vias and by determining the degree of via filling.