DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.contributor.author | Song, BS | ko |
dc.contributor.author | Bacrania, K | ko |
dc.date.accessioned | 2013-03-06T06:18:52Z | - |
dc.date.available | 2013-03-06T06:18:52Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2007-03 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.42, pp.475 - 485 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/86107 | - |
dc.description.abstract | Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 mu W/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for I- and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0 degrees to 85 degrees C and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1.1 x 1.3 mm(2) using a 0.18-mu m complementary metal oxide semiconductor (CMOS) process. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CMOS ADC | - |
dc.subject | A/D CONVERTER | - |
dc.subject | SFDR | - |
dc.title | A 10-bit 50-MS/s pipelined ADC with opamp cuffent reuse | - |
dc.type | Article | - |
dc.identifier.wosid | 000245110400002 | - |
dc.identifier.scopusid | 2-s2.0-33847752977 | - |
dc.type.rims | ART | - |
dc.citation.volume | 42 | - |
dc.citation.beginningpage | 475 | - |
dc.citation.endingpage | 485 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2006.891718 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Song, BS | - |
dc.contributor.nonIdAuthor | Bacrania, K | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | capacitor-array multiplying digital-to-analog converter (MDAC) | - |
dc.subject.keywordAuthor | digital-to-analog converter (DAC) | - |
dc.subject.keywordAuthor | low-power technique | - |
dc.subject.keywordAuthor | opamp-sharing | - |
dc.subject.keywordAuthor | pipelined analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | switched-opamp | - |
dc.subject.keywordPlus | CMOS ADC | - |
dc.subject.keywordPlus | A/D CONVERTER | - |
dc.subject.keywordPlus | SFDR | - |
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