DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yang, BD | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2013-03-04T21:16:16Z | - |
dc.date.available | 2013-03-04T21:16:16Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2003-08 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.11, pp.590 - 600 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/84173 | - |
dc.description.abstract | This paper describes a newly proposed low-power charge-recycling read-only memory (CR-ROM) architecture. The CR-ROM reduces the power consumption in bit lines, word lines, and precharge lines by recycling the previously used charge. In the proposed CR-ROM, bit-line swing voltage is lowered by the charge recycling between bit lines. When N bit lines recycle their charges, the swing voltage and the power of the bit lines become 1/N and 1/N-2 compared to the conventional ROMs, respectively. As the number of N increases, the power saving in bit lines becomes salient. Also, power consumption in word lines and precharge lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the CR-ROM consumes 60%similar to85% of the conventional low-power ROMs with 1 K x 32 b. A CR-ROM with 32 kb was implemented in a 0.35-mum CMOS process. The power dissipation is 6.60 mW at 100 MHz with 3.3 V and the maximum operating clock frequency is 150 MHz. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | BUS ARCHITECTURE | - |
dc.title | A low-power charge-recycling ROM architecture | - |
dc.type | Article | - |
dc.identifier.wosid | 000185247100006 | - |
dc.identifier.scopusid | 2-s2.0-0141527492 | - |
dc.type.rims | ART | - |
dc.citation.volume | 11 | - |
dc.citation.beginningpage | 590 | - |
dc.citation.endingpage | 600 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Yang, BD | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | bit line | - |
dc.subject.keywordAuthor | charge recycling | - |
dc.subject.keywordAuthor | low-power design | - |
dc.subject.keywordAuthor | read-only memory (ROM) | - |
dc.subject.keywordAuthor | very large scale integration (VLSI) | - |
dc.subject.keywordAuthor | design | - |
dc.subject.keywordAuthor | word line | - |
dc.subject.keywordPlus | BUS ARCHITECTURE | - |
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