TLB update-hint: A scalable TLB consistency algorithm for cache-coherent non-uniform memory access multiprocessors

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dc.contributor.authorSeong, Bko
dc.contributor.authorKim, Dong-Gookko
dc.contributor.authorRoh, Yko
dc.contributor.authorPark, Kyu-Hoko
dc.contributor.authorPark, Dae-Yeonko
dc.date.accessioned2013-03-04T19:07:05Z-
dc.date.available2013-03-04T19:07:05Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2004-07-
dc.identifier.citationIEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E87D, pp.1682 - 1692-
dc.identifier.issn0916-8532-
dc.identifier.urihttp://hdl.handle.net/10203/83759-
dc.description.abstractShared memory multiprocessors in which each processor has its own TLB must manage consistency among TLBs and a page table. As the large-scale CC-NUMA (cache-coherent non-uniform memory access) shared memory multiprocessors become popular, it is important for TLB consistency management algorithms to be highly scalable. In this paper, we propose a TLB update-hint algorithm as a scalable TLB consistency management solution for CC-NUMA multiprocessors. By using a lazy TLB invalidation approach, we reduced the number of unnecessary processor interruptions and idle-waiting time, and achieved a high level of scalability. Using a shared memory simulator, we evaluated the TLB update-hint algorithm. For performance comparison, we also simulated the TLB shootdown algorithm, one of the most popular TLB consistency algorithms. The simulations demonstrated that the TLB update-hint algorithm scales well in systems with a large number of processors. At 64 node systems, the TLB update-hint algorithm shows 47similar to87% better performance than the TLB shootdown algorithm.-
dc.languageEnglish-
dc.publisherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG-
dc.subjectVIRTUAL-ADDRESS CACHES-
dc.titleTLB update-hint: A scalable TLB consistency algorithm for cache-coherent non-uniform memory access multiprocessors-
dc.typeArticle-
dc.identifier.wosid000222585200010-
dc.identifier.scopusid2-s2.0-3142782790-
dc.type.rimsART-
dc.citation.volumeE87D-
dc.citation.beginningpage1682-
dc.citation.endingpage1692-
dc.citation.publicationnameIEICE TRANSACTIONS ON INFORMATION AND SYSTEMS-
dc.contributor.localauthorPark, Kyu-Ho-
dc.contributor.localauthorPark, Dae-Yeon-
dc.contributor.nonIdAuthorSeong, B-
dc.contributor.nonIdAuthorRoh, Y-
dc.type.journalArticleArticle; Proceedings Paper-
dc.subject.keywordAuthorTLB consistency-
dc.subject.keywordAuthorTLB shootdown-
dc.subject.keywordAuthorcache-coherent non-unifrom memory access-
dc.subject.keywordAuthorshared memory multiprocessor operating system-
dc.subject.keywordPlusVIRTUAL-ADDRESS CACHES-
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EE-Journal Papers(저널논문)RIMS Journal Papers
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