DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Soontae | ko |
dc.contributor.author | N. Vijaykrishnan | ko |
dc.contributor.author | M. Kandemir | ko |
dc.contributor.author | A. Sivasubramaniam | ko |
dc.contributor.author | M. J. Irwin | ko |
dc.date.accessioned | 2013-03-04T16:28:27Z | - |
dc.date.available | 2013-03-04T16:28:27Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2003-05 | - |
dc.identifier.citation | ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, v.2, no.2, pp.163 - 185 | - |
dc.identifier.issn | 1539-9087 | - |
dc.identifier.uri | http://hdl.handle.net/10203/83272 | - |
dc.description.abstract | The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for low-power systems. In many media and embedded applications, the memory system can consume more than 50% of the overall system energy, making it a ripe candidate for optimization. To address this increasingly important problem, this article studies energy-efficient cache architectures in the memory hierarchy that can have a significant impact on the overall system energy consumption.Existing cache optimization approaches have looked at partitioning the caches at the circuit level and enabling/disabling these cache partitions (subbanks) at the architectural level for both performance and energy. In contrast, this article focuses on partitioning the cache resources architecturally for energy and energy-delay optimizations. Specifically, we investigate ways of splitting the cache into several smaller units, each of which is a cache by itself (called a subcache). Subcache architectures not only reduce the per-access energy costs, but can potentially improve the locality behavior as well.The proposed subcache architecture employs a page-based placement strategy, a dynamic page remapping policy, and a subcache prediction policy in order to improve the memory system energy behavior, especially on-chip cache energy. Using applications from the SPECjvm98 and SPEC CPU2000 benchmarks, the proposed subcache architecture is shown to be very effective in improving both the energy and energy-delay metrics. It is more beneficial in larger caches as well. | - |
dc.language | English | - |
dc.publisher | Assoc Computing Machinery | - |
dc.title | Partitioned Instruction Cache Architecture For Energy Efficiency | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.citation.volume | 2 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 163 | - |
dc.citation.endingpage | 185 | - |
dc.citation.publicationname | ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | - |
dc.contributor.localauthor | Kim, Soontae | - |
dc.contributor.nonIdAuthor | N. Vijaykrishnan | - |
dc.contributor.nonIdAuthor | M. Kandemir | - |
dc.contributor.nonIdAuthor | A. Sivasubramaniam | - |
dc.contributor.nonIdAuthor | M. J. Irwin | - |
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