Design of a New Low-power 2.4 GHz CMOS LNA

Abstract

A 2.4-GHz single-stage CMOS low noise amplifier (LNA) structure with ultra low power consumption is proposed. A current reuse technique is used to decrease power dissipation with increasing amplifier transconductance for the LNA. Thus, the same amplifier transconductance for the LNA will be achieved at decreased power dissipation. Also, due to the use of inverter-type amplifier which has a symmetric structure, the proposed LNA has high linearity. The designed 2.4- GHz LNA using 0.25-mum CMOS technology achieves a power gain of 14.7 dB, a noise figure of 2.5 dB, and an IIP3 of 0.5 dBm even at a power consumption of 1.97 mW.